1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device and more particularly to a process for manufacturing a semiconductor device that has a substrate and surface channel and buried channel insulated gate field effect transistors of a first conductive type and surface channel and buried channel insulated gate field effect transistors of a second conductive type formed on the substrate.
2. Description of the Related Art
MOSFETs have channel structures of the surface channel and buried channel types. The surface channel type is used for both nMOSs and pMOSs in a CMOS process for digital circuits because it is relatively easy to suppress its short channel effect. In the surface channel MOS, however, carriers are scattered in an interface between a silicon substrate and an oxide film, causing relatively high levels of noise. On the other hand, in the buried channel MOS, a channel is formed within a silicon substrate to lower the level of noise . Therefore, the buried channel type is more suitable for analog circuits than the surface channel type.
Important structural differences between the surface channel MOS and the buried channel MOS will be described below. In the surface channel type, there is a difference in dopant type between a substrate or well region and a polysilicon gate electrode. On the other hand, in the buried channel type, there is no difference in dopant type between a substrate or well region and a polysilicon gate electrode. For example, in the surface channel nMOS, a well region is of the p type and a polysilicon gate electrode is of the n+ type. On the other hand, in the buried channel nMOS, a well region is of the p type and a polysilicon gate electrode is of the p+ type.
FIGS. 5A-5C and 6D-6F show conventional process steps for manufacturing the surface channel MOS and buried channel MOS in the art.
As shown in FIG. 5A, device isolation regions 2 are formed on a p-type silicon substrate 1 and a sacrificial oxide film 3 is grown thereon. Then, a p well 4 is formed within an nMOS-forming region; an n well 5, within a pMOS-forming region.
First boron implantation for controlling a threshold level is performed into a surface channel nMOS-forming region on the p well 4 to make the region into a more positive region in terms of dopant concentrations in order to form an nMOS surface channel region 6. First arsenic implantation for controlling a threshold level is performed into a surface channel pMOS-forming region on the n well 5 to make the region into a more negative region in terms of dopant concentrations in order to form a pMOS surface channel region 7 as well.
Second arsenic implantation for controlling a threshold level is performed into a buried channel nMOS-forming region on the p well 4 to form an nMOS buried channel region 8 at a depth of 50-150 nm beneath the silicon surface by inverting the p well 4 into an n-type region. Second boron implantation for controlling a threshold level is performed into a buried channel pMOS-forming region on the n well 5 to form a pMOS buried channel region 9 at a depth of 50-150 nm beneath the silicon surface as well by inverting the n well 5 into a p-type region.
As shown in FIG. 5B, after removing of the sacrificial oxide film 3, a gate oxide film 10 is grown, a non-doped polysilicon 21 is further grown and then a resist is patterned by photolithography.
Next, the non-doped polysilicon 21 is etched to form non-doped polysilicon electrodes 22 as shown in FIG. 5C.
As shown in FIG. 6D, SD (source/drain)-arsenic is selectively implanted into the non-doped polysilicon electrode 22 and diffused layer-forming region of the surface channel nMOS, the diffused layer-forming region of the buried channel nMOS and the non-doped polysilicon electrode 22 of the buried channel pMos.
A resist that covers the non-doped polysilicon electrode 22 of the buried channel nMOS is located inwardly by a certain margin from the edge of the non-doped polysilicon electrode 22 so that n+ source/drain regions 18 may not be offset from the non-doped polysilicon electrode 22.
A resist that covers the diffused layer of the buried channel pMOS is also located inwardly by a certain margin from the edge of the non-doped polysilicon electrode 22 so that implanted SD-arsenic may not reach the diffused layer.
As shown in FIG. 6E, SD-boron is selectively implanted into the non-doped polysilicon electrode 22 and diffused layer-forming region of the surface channel pMOS, the diffused layer-forming region of the buried channel pMOS and the non-doped polysilicon electrode 22 of the buried channel nMOS.
A resist that covers the non-doped polysilicon electrode 22 of the buried channel pMOS is located inwardly by a certain margin from the edge of the non-doped polysilicon electrode 22 so that p+ source/drain regions 19 may not be offset from the non-doped polysilicon electrode 22.
A resist that covers the diffused layer of the buried channel nMOS is also located inwardly by a certain margin from the edge of the non-doped polysilicon electrode 22 so that implanted SD-boron may not reach the diffused layer.
Next, the arsenic and boron are heated to activate as shown in FIG. 6F.
The activation leads to the formation of the n+ source/drain regions 18 of the surface channel nMOS and buried channel nMOS and the p+ source/drain regions 19 of the surface channel pMOS and buried channel pMOS. The non-doped polysilicon electrode 22 of the surface channel nMOS becomes an n+ polysilicon gate electrode 23 with added SD-arsenic. The non-doped polysilicon electrode 22 of the surface channel pMOS becomes a p+ polysilicon gate electrode 24 with added SD-boron. The non-doped polysilicon electrode 22 of the buried channel nMOS becomes a p+ polysilicon gate electrode 25 with added SD-boron. The non-doped polysilicon electrode 22 of the buried channel pMOS becomes an n+ polysilicon gate electrode 26 with added SD-arsenic.
A conventional method for manufacturing the surface channel MOS and buried channel MOS is disclosed as mentioned above. As shown in FIG. 6F, however, there are regions into which SD-arsenic is implanted but SD-boron is not implanted at both ends of the p+ polysilicon gate electrode 25 of the buried channel nMOS. The regions become, after heat treatment, pxe2x88x92 polysilicon regions 27 with relatively low concentrations of p-type dopant because boron atoms diffused from the central portion of the SD-boron-implanted gate polysilicon compensate SD-arsenic-implanted portions. Similarly, there are n polysilicon regions 28 with relatively low concentrations of n-type dopant at both ends of the n+ polysilicon gate electrode 26 of the buried channel pMOS.
In the buried channel nMOS, a pxe2x88x92 polysilicon region 27 of low dopant concentration originally differs in work function from a p+ polysilicon gate electrode 25 of originally high dopant concentration. As a result, the central portion of the transistor, which is covered with the p+ polysilicon electrode 25, disadvantageously differs in threshold level from the edge portion of the transistor, which is covered with the p+ polysilicon region 27. A sheet resistance of the whole gate polysilicon electrode may be larger than that of a gate polysilicon electrode consisting only of the p+ polysilicon electrode 24 on the surface channel pMOS. If silicide formation is performed to lower the sheet resistances of gate polysilicon electrodes and diffused layers, the polysilicon electrodes with different concentrations of a dopant are difficult to silicify uniformly because the silicide formation reaction between a metal and silicon depends greatly on the concentration of a dopant present in silicon. The above-mentioned disadvantages also apply to the buried channel pMOS.
Japanese Patent Publication No.5-56022 discloses a technique to make the conductive type of a gate electrode of the buried channel MOS transistor into the opposite conductive type to that of the channel type. Japanese Patent Application Laid-open No.61-174664 discloses a process comprising forming a p-type dopant-introduced polysilicon layer throughout the surface, patterning the layer to form gate electrodes, then implanting arsenic ions as the n-type dopant for forming source/drain regions of an n-channel MOS transistor, and implanting arsenic ions as the p-type dopant for forming source/drain regions of a p-channel MOS transistor, so that these regions are converted into the buried channel type and the surface channel type, respectively.
Accordingly, it is an object of the present invention is to provide a process for manufacturing a semiconductor device that has a substrate and surface channel and buried channel insulated gate field effect transistors of a first conductive type and surface channel and buried channel insulated gate field effect transistors of a second conductive type formed on the substrate.
The process comprises introducing a dopant of the first conductive type prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel insulated gate field effect transistor of the first conductive type and the buried channel insulated gate field effect transistor of the second conductive type. The process further comprises introducing a dopant of the second conductive type prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel insulated gate field effect transistor of the second conductive type and the buried channel insulated gate field effect transistor of the first conductive type.
Other features and advantages of the invention will be apparent from the following description of the preferred embodiments thereof.